LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity BCDA7Segmentos is
  PORT (D:IN std_logic_vector(3 DOWNTO 0);
  O:OUT std_logic_vector(7 DOWNTO 0));
end;

architecture aBCDA7Segmentos OF BCDA7Segmentos IS
BEGIN
  PROCESS (D)
  BEGIN
    CASE D IS
      WHEN "0000"=>O<="00000011";
      WHEN "0001"=>O<="10011111";
      WHEN "0010"=>O<="00100101";
      WHEN "0011"=>O<="00001101";
      WHEN "0100"=>O<="10011001";
      WHEN "0101"=>O<="01001001";
      WHEN "0110"=>O<="01000001";
      WHEN "0111"=>O<="00011111";
      WHEN "1000"=>O<="00000001";
      WHEN "1001"=>O<="00001001";
      WHEN OTHERS=>O<="00000000";
    end CASE;
  end PROCESS;
end;
